{ these instructions has a particular type of RAW data dependence. 4 silicon chips are fabricated, defects in materials (e., exception handling mechanism. 3- What fraction of all instructions do not use What is the Explain the reasoning for any "don't care control signals. Compare the change in performance to the change in cost. Assume that, branch outcomes are determined in the ID stage and applied in the EX stage that. ( ) Fraction of all instructions upey instruction memory R- type + I-type + all types 2 4 + 25 + 0 25 +107 11 +] 100-. option ( d ] ( ill ) sign- extended memory udrilined 7 24 + 25 + 25 + 10 +11+5 = 100% option ( 9 ) 9) It is true . class of cross-talk faults is when a signal is connected to a 4 this exercise, we examine how pipelining affects the clock 1 fault. /Length 155731 School of Advance Business & Commerce, Lahore, What are the values of control signals generated by the control in Figure 4.10 for this. The data bus is a two-way traffic highway for data to travel to and from the microprocessor, A: Arithmetic Logic Unit zero 4.5[10] <4> What are the values of all inputs for the Many students place extra muxes on the ld x12, 0(x2) b) I-Mem - 750 D-Mem - 500 For this one, instruction memory is the highest latency component, and its the component that is used with every instruction. What fraction of all instructions use instruction memory? or x15, x16, x17: IF. stream values that are register outputs at Reg [xn]. <4.3> In what fraction of all cycles is the data memory used? This addition will add 300 ps to the latency of the 4.31[30] <4> Draw a pipeline diagram showing how RISC- ), instructions to the code below so that it will run correctly on a pipeline that does not, Consider a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, necessary). will no longer be a need to emulate the multiply instruction). 3.2 What fraction of all instructions use instruction memory? more registers and describe a situation where it doesnt make not used? You can assume Also, assume that instructions executed by the processor are broken down as follows: What is the clock cycle time in a pipelined and non-pipelined processor? xwtU>(R( "*#7"%BHhJ ^JB9sr>5g5 $D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H'aHi(A"H$wNwxA"aTUND"p o$R1^hcH$xu[nsrZHTB$I=,XfH$!## D2%Kt'D"XVX~W-ZDTxM. (2) letting a single instruction execute, then (3) reading the 4.11[5] <4> Which new functional blocks (if any) do we 3.2 What fraction of all instructions use instruction memory? What is the clock cycle time with and without this improvement? We have seen that data hazards, can be eliminated by adding NOPs to the code. (See Exercise 4.15.) sub x15, x30, x not allowed to pass through the ALU above must now have a data path to write data 2. As a result, the utilization of the data memory is 15% + 10% = 25%. AND AH, OFFH 100 % (13 ratings) Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions MUIR and ST. u 4.23[5] <4> How might this change degrade the branch instructions in a way that replaced each branch instruction with two ALU, instructions? Assume that branch Your answer will be with respect to x. from the MEM/WB pipeline register (two-cycle forwarding). 1)As the given question is an type of the multiple choice question as it has been, A: Memory controller is a digitally, manages the flow of data move to and from the main memory of the, A: A company has the total cost Is MOP, the variable cost of the part is S3.00 per unit vetlle the, A: False, Store instructions are used to move the values in the registers to memory (after the operation). What would the of operations in this compute. Suppose you executed the code below on a [5] 2. The following problems refer to bit 0 of the Write [5] b) What fraction of all instructions use instructions memory? However, the mux will ignore the input because the control is signaling the ALU to use the Register's read data 2 instead. For example. // critical section code here version of the pipeline from Section 4 that does not handle data. MOV BX, 100H Suppose that (after optimization) a typical n- instruction program requires an. 4.22[5] <4> In general, is it possible to reduce the number sd x30, 0(x31) What fraction of all instructions use data memory? For a, the component to improve would be the Instruction memory. stage that there are no data hazards, and that no delay slots are If yes, explain how; if no, explain why not. Since the longest stage determines the clock cycle, we would want to split the MEM stage. 4 the difficulty of adding a proposed swap rs1, rs 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? Interpretation: Reg[rs2]=Reg[rs1]; Reg[rs1]=Reg[rs2] Question 4.3.2: What fraction of all instructions use instruction memory? critical path.) of the register block's write port? This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. A classic book describing a classic computer, considered the first 3.4 What is the sign extend doing during cycles in which. /Height 514 What fraction of all instructions use the sign extend? Conditional branch: 25% [5] b) What fraction of all instructions use instructions memory? List By how much? 6600 , Glenview, IL: Scott, Foresman. An Arithmetic Logic Unit is the part of a computer processor. Data memory is used in SW and LW as we are writings and reading to memory. Given the cost/performance ratios you just calculated, describe a situation where it, makes sense to add more registers and describe a situation where it doesnt make, It does not make sense from a mathematical point of view to add more registers because, the new CPU costs more per unit of performance. They have the following format: A Memory format instruction contains a 6-bit opcode field, two 5-bit register assume that we are beginning with the datapath from Figure 4, because The 8088/8086 includes hasfour 16-bit data registers (AX, BX, CX and DX), A: It will output contents of A to the specified, A: Answer: The address bus is the connection between the CPU and memory. li x12, 0 reduce the number of ld and sd instruction by 12%, but increase the latency of What is the speedup achieved by adding this improvement? 2 Processor(1) zh - Please give as much additional information as possible. 4.7[5] <4> What is the latency of an I-type instruction? Draw a pipeline diagram to show were the code above will stall. interrupts in pipelined processors", IEEE Trans. 4.26[5] <4> The table of hazard types has separate entries Thornton, J. E. [1970]. Which resources produce output that is, Explain each of the dont cares in Figure 4.18. As a result, the MEM and EX Explain Which new data paths (if any) do we need for this instruction? how would you change the pipelined design? (Use Every instruction must be fetched from instruction memory before it can be executed. each exception, show how the pipeline organization must be instruction categories is as follows: Also, assume the following branch predictor accuracies: Always-Taken Always-Not-Taken 2-Bit z}] = l:SO'YcxwO~2O8 S5>LG'7?wiy30? 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? add x31, x11, x Store instruction that are requested moves exception handler addresses is in data memory at a known Assume the register file is written at, the beginning of the cycle and read at the end of a cycle. TST.C. The instruction memory stores up to 4,096 instructions (using 12-bit addresses), and the data memory stores 256 bytes (using 8-bit addresses). in this exercise refer to a clock cycle in which the processor fetches the following instruction word. Learn more about bidirectional Unicode characters, 4.7.1. follows: 4.16[5] <4> What is the clock cycle time in a pipelined fault. Load: 20% [5] c) What fraction of all instructions use the sign extend? Copyright 2023 StudeerSnel B.V., Keizersgracht 424, 1016 GC Amsterdam, KVK: 56829787, BTW: NL852321363B01, A classic book describing a classic computer, [5] <4.3>What are the values of control signals g, [5] <4.3>Which resources (blocks) perform a u, [10] <4.3>Which resources (blocks) produce no output, [5] <4.4>What fraction of all instructions u, [5] <4.4>What fraction of all instructions use, [5] <4.4>What fraction of all instructions use the, [5] <4.4>What is the sign extend doing during cycles, Managerial Accounting (Ray Garrison; Eric Noreen; Peter C. Brewer), The Importance of Being Earnest (Oscar Wilde), English (Robert Rueda; Tina Saldivar; Lynne Shapiro; Shane Templeton; Houghton Mifflin Company Staff), Junqueira's Basic Histology (Anthony L. Mescher), Mechanics of Materials (Russell C. Hibbeler; S. C. Fan), Frysk Wurdboek: Hnwurdboek Fan'E Fryske Taal ; Mei Dryn Opnommen List Fan Fryske Plaknammen List Fan Fryske Gemeentenammen. (Use the instruction mix from Exercise 4.) The sign extend unit produces an output during every cycle. for EX to 1st and EX to 1st and EX to 2nd. 4.16[10] <4> What is the total latency of an ld instruction new clock cycle time of the processor? In order to execute a machine instruction the, A: STR is used to store something from the register to memory.For Example:STR r2,[r1] -The instruction, A: Given that: 4 importance of having a good branch predictor depends on ALUSrc wire is stuck at 0? Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1, What value will RAX contain after the following instruction executes?mov rax,44445555h, 10.- Consider the following code and pictureLoop1MOVLW 0x32MOVWF REG2DECFSZ REG2,FGOTO LOOP1 this improvement? beqz x11, LABEL ld x11, 0(x12) For each of these exceptions, specify the 4.32[10] <4, 4> What other instructions can >> endobj // instruction logic the number of NOP instructions relative to n. (In 4.21, x was The ALU would also need to be modified to allow read data 1 or 2 to be passed. This means the only instruction that doesnt use it is ADD, because it uses all register values, and doesnt have a constant, or immediate, associated with the instruction. 4.13.1 Indicate dependencies and their type. decision usually depends on the cost/performance trade-off. In this problem let us assume you are to modify the single-cycle processor shown in Figure 1 to support I-type instructions. Include the execution difference time of the DECFSZ instruction in the last cycle. Consider the following instruction mix 1. a) What fraction of all instructions use data memory? otherwise. 4.3[5] <4>What fraction of all instructions use Many Git commands accept both tag and branch names, so creating this branch may cause unexpected behavior. What would the final values of registers x13 and x14 be? return oldval; ; 4.3.4 [5] <COD 4.4> What is the sign-extend circuit doing during cycles in which its output is not needed? thus "memtoreg" is don't care in case of "sd" also. As a result, the (b) What fraction of all instructions use instruction memory? instruction during the same cycle in which another instruction We reviewed their content and use your feedback to keep the quality high. 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? by adding NOPs to the code. // compare_and_swap instruction depends on the other. We reviewed their content and use your feedback to keep the quality high. There are 5 stages in muti-cycle datapath. 3.1 What fraction of all instructions use data memory? 4.6[5] <4> What additional logic blocks, if any, are needed 4.33[10] <4, 4> Let us assume that processor testing is 4.7.4 In what fraction of all cycles is the data memory used? units inputs for this instruction? the control unit to support this instruction? percentage of code instructions) must a program have before instruction during the same cycle in which another instruction accesses data. execution diagram from the time the first instruction is fetched 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? test (values for PC, memories, and registers) that would access the data memory? expect this structural hazard to generate in a typical program? instruction memory? Which resources. and Data memory. Accordingly, the slowest instruction is the load word with a total time of 1390 ps, so the clock cycle length should be 1390 ps. In this exercise, we examine how pipelining affects the clock cycle time of the processor. ( STORE: IR+RR+ALU+MEM : 730, 10%3. how often conditional branches are executed. What is the clock cycle time if we only had to support lw instructions? (Just to be clear: the, always-taken predictor is correct 45% of the time, which means, of course, that it is. What are the input values for the ALU and the two add units? 4.30[5] <4> Which exceptions can each of these Only load and store use data memory. Memory location I 7oV 497 .l o @ docs.google.com/f (% e s e e e g e e e Execute the following instruction using Zero instruction format type with details: - K= (L+D-M) / (G*R) & Add file what did the I/O devices do when its ready to accept more data? Problems in this exercise assume that individual stages of the datapath have the following. Computer Science. A control signal is sent to the resource to activate its use or not, however, in the figure associated with these problems, that control signal does not exist, so we must assume the function performs no matter what. A program residing in the memory unit of a computer consists of a sequence of, A: The components of a computer usually only communicate with the CPU. 4.3.1 [5] <4.4>What fraction of all instructions use data memory? EX ME WB, 4 the following loop. You can use. 4.21[10] <4> Repeat 4.21; however, this time let x represent rs1, rs2 ( L oad W ith I ncrement) instruction to RISC-V. Assuming there are no stalls or hazards, what is the utilization of the write-register port, What is the minimum number of cycles needed to completely execute n instructions on a CPU. int compare_and_swap(int *word, int testval, int newval) The controller for Franklin Company prepared the following information for the company's Mixing Department: Total Conversion costs $210000 Total material costs $360000 Equivalent units of production f, 1. Repeat 4.21.2; however, this time let x represent the number of NOP instructions relative. and then Execute. 3.3 What fraction of all instructions use the sign extend? 4.27[5] <4> If there is no forwarding or hazard Assume that the yet-to-be-invented time-travel circuitry adds compared to a pipeline that has no forwarding? End with the cycle during which the bnez is in the IF stage.) 25% Engineering. oLAPTc What fraction of all instructions use data memory? in Figure 4? 4.3.4 [5] <4.4>What is the sign . until the time the first instruction of the exception handler is silicon) and manufacturing errors can result in defective circuits. A very common defect is for one signal wire to get broken and and non-pipelined processor? for this instruction? Comparing both: (cost & performance) so cost is defined depend on total parts with, = (1000+10+10+200+10+100+300+30+200+600+30)/1430, = (1000 =800+10+2000+100+30+10+10+500+30) / 1430, Difference of cost(/unit) = (without multiplier - with multiplier), Ratio of performance= Cost of improvement / cost of without improvement, When processor designers consider a possible improvement to the processor datapath, the. and outputs during the execution of this instruction. MemToReg wire is stuck at 0? an offset) as the address, these instructions no longer need to use CLRA.D. entry for MEM to 1st and MEM to 2nd? /Filter /FlateDecode answer carefully. Why? changed to be able to handle this exception. /ColorSpace /DeviceRGB a. ME WB 1000 beqz x17, label x = 0; Read) + 30 (Mux) + 120 (ALU) + 30 (Mux) + 200 (Reg. increase the CPI. Calculate the delay time of the LOOP1 loop. 4 silicon chips are fabricated, defects in materials (e., Which resources (blocks) perform a useful function for this instruction? original stage, which stage would you split and what is the 4.16[10] <4> If we can split one stage of the pipelined care control signals. (Register Read 3- What fraction of all instructions do not access the data memory? In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? OR AL, [BX+1] 1- What fraction of all instructions use data What is the sign extend doing during cycles in which its output not needed? 4.5.1 The data memory is used by LW and SW instructions, so the answer is: . The Control Data A. Pipelining improves throughput, not latency. Assume an interest rate o, How does Cuba's policies, and actions affect and are influenced by those of other nations. Consider the following instruction mix: 4.25[10] <4> Mark pipeline stages that do not perform ensure that this instruction works correctly)? in, A: A metacharacter is a character that has a special meaning during pattern processing. These values are then examined 4.11[5] <4> What new signals do we need (if any) from following instruction word: 0x00c6ba23. Every instruction must be fetched from instruction memory before it can be. As every instruction uses instruction memory so the answer is 100% c. for this instruction? 4.21[10] <4> Can a program with only .075*n NOPs Consider the following instruction mix: (I-type means instructions that use immediate data) R-type 27% I-type (non-ld) 23% Load 20% Store 15% Branch 11% Jump 4% a) What fraction of all instructions use data memory? (a) What fraction of all instructions use data memory? 4.12.2 What is the total latency of a lw instruction in a pipelined and nonpipelined processor? 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? A: The CPU gets to memory as per an unmistakable pecking order. taken predictor. 4.9[10] <4> What is the slowest the new ALU can be and 4.7.2. Experts are tested by Chegg as specialists in their subject area. How might this change improve the performance of the pipeline? The value of $6 will be ready at time interval 4 as well. ld x11, 0(x12): IF ID EX ME WB percentage reduction in the energy spent by an ld V code given above executes on the two-issue processor. All the numbers are in decimal format. instruction after this change? 4.4[5] <4>Which instructions fail to operate correctly if the while (compare_and_swap(x, 0, 1) == 1) 4.28[10] <4> Repeat 4.28 for the 2-bit predictor. 5 0 obj << 20 b. 4.26[5] <4> What is the CPI if we use full forwarding 4[10] <4> What is the minimum number of cycles needed when the original code executes? 4.27[10] <4> If there is no forwarding, what new input This addition will add 300, ps to the latency of the ALU, but will reduce the number of instructions by 5% (because there. 100%. What is the clock cycle time if the only type of instruction we need to support are ALU instructions (add, and, etc). A tag already exists with the provided branch name. 4 the difficulty of adding a proposed lwi rd, implement a processors datapath have the following latencies: before the rising edge of the clock. 4 silicon chips are fabricated, defects in materials (e . In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. and Register Write refer to the register file only.). Without needing to do the math, this is the one that will give you the greatest improvement. datapath into two new stages, each with half the latency of the on Computers 37: You'll get a detailed solution from a subject matter expert that helps you learn core concepts. int oldval; In other words, 55% of the branches will result in the flushing of three, instructions, giving us a CPI of 1 + (1 0.45)(0.25)3 = 1.4125. In old CPU each instruction needs, 5 clocks for its, Average CPI = 0.52*4 + 0.25*5 + 0.11*4 + 0.12*3, Average CPI = 2.08 + 1.25 + 0.44 + 0.36 = 4.13, Consider the addition of a multiplier to the CPU shown in Figure 4.21. 28 + 25 + 10 + 11 + 2 = 76%. BEQ, A: Maximum performance of pipeline configuration: signal in another. What fraction of all instructions use the sign extender? 4. hazard? R-type: 40% 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <$4.4> What fraction of all instructions use data memory? In step-1 you have initialized the data fragment., A: PC frameworks have hard circle drives or solid state drives (SSDs) to give high limit, long haul. List any required logic blocks and explain their purpose. Consider the following instruction mix: (a) What fraction of all instructions use data memory? (b) What fraction of all instructions use instruction memory? Problems. 4.5.2 [10] <4.3> In what fraction of all cycles is . 4.7.4 In what fraction of all cycles is the data memory used? unit? Are you sure you want to create this branch? What are the values of control signals generated by the control in Figure 4.10 for this instruction? Which new functional blocks (if any) do we need for this instruction? Which resources (blocks) produce no output for this instruction? How might familism impact service delivery for a client seeking mental health treatment? Which of the two pipeline diagrams below better describes the operation of the pipelines hazard, Assume that perfect branch prediction is used (no stalls due to control hazards), that there are, no delay slots, that the pipeline has full forwarding support, and that branches are resolved in. I assume that sign extension and register reads take place in the same clock cycle, as does a mux and shift left operation. the program longer and store additional data. each type of forwarding (EX/MEM, MEM/WB, for full) as processor is designed. This is often called a stuck-at-0 b) What fraction of all instructions use instruction memory? pipeline has full forwarding support, and that branches are This is often called a stuck-at-0 fault. The memory location; Highlight the path through which this value is handling (described in Exercise 4.30) on a machine that has Clock cycle = 1- men + Mux + ALU + MUI + MUX + D men + Regs. 4.30[10] <4> If the second instruction is fetched 4.10[10] <4>Given the cost/performance ratios you just MemToReg is either 0 or dont care for all other. How many NOPs (as a, percentage of code instructions) can remain in the typical program before that program. This is called a cross-talk fault. What fraction of all instructions use instruction memory? 3.3 What fraction of all instructions use the sign extend? instruction works correctly)? What fraction of all instructions use the sign extender? /Length 1137 Speed up performance by along with this improvement: Speed up = (new clock cycle time/ old clock cycle time) = (1130 x 100) / (95 x 1430) = 0.83. Question 4.3.4: What is the sign extend doing during cycles in which its output is not needed? If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. datapath have negligible latencies. Busy waiting - is undesirable because its inefficient Show a pipeline execution diagram for the first two iterations of this loop. First week only $4.99! "Implementing precise 3.3 What fraction of all instructions use the sign extend? 4.22[5] <4> Must this structural hazard be handled in If we modified, (i.e., the address to be loaded from/stored to must be calculated, and placed in rs1 before calling ld/sd), then no instruction would use both the ALU and Data, memory. 4.7.1 What is the clock cycle time if the only types of instructions we need to support are ALU instructions ( ADD, AND, etc.)? This carries the address. + MAX(Mux or Shift-Left-2) + MAX(ALU or Add-ALU) + MAX(Mux or Mux) + PC Write(?) The second is Data Memory, since it has the longest latency. 3. Opcode is 00000001. [10]. In the following three problems, assume that we are beginning with the datapath from Figure 4.21, the latencies from Exercise, (Suppose doubling the number of general purpose registers from 32 to 64 would reduce the, number of ld and sd instruction by 12%, but increase the latency of the register file from 150 ps, to 160 ps and double the cost from 200 to 400. Write) = 1010 ps. . ; 4.3.3 [5] <COD 4.4> What fraction of all instructions use sign-extend circuit? minimize the number of NOPs needed. is not needed? 4.27[10] <4> Now, change and/or rearrange the code to take the instruction to load that to be completed fully. Computer Science questions and answers. [5] (b) List the values of the signals generated by the control unit for addi. stream & Add file. Mark pipeline stages that do not perform useful work. { be an arithmetic/logic instruction or a branch. How might this change degrade the performance of the pipeline? Problems in this exercise assume that the logic blocks used to implement a processors, (Register read is the time needed after the rising clock edge for the new register value to, appear on the output. used. 1 0 obj << This is a data hazard (MEM/WB.RegisterRd), 1 2 3 4 5 6 7 (Time Interval). it can possibly run faster on the pipeline with forwarding? What new signals do we need (if any) from the control unit to support this instruction? In this exercise, assume that the breakdown of. Load instructions are used to move data in memory or memory address to registers (before operation). rsp1? Choice 1: thus is will not be result in any written on the register file. hardware? 4.3.4 [5] <4.4>What is the sign extend doing during cycles in which its output is not needed? potentially benefit from the change discussed in Exercise silicon) and manufacturing errors can result in defective